![]() The digital inputs should generally be between DGND − 0.3 V and V IO+ 0.3 V to avoid violating the absolute maximum ratings. ![]() This pin should be at the same voltage as the host interface (MCU, DSP, or FPGA) supply. Most SAR ADCs provide a separate digital I/O power-supply input, V IO or V DRIVE, which determines the operating voltage and logic compatibility of the interface. Digital I/O Power-Supply Level and Sequence This article discusses design techniques for reliable, integrated digital interfaces, including the digital power-supply level and sequence, I/O state during turn on, interface timing, signal quality, and errors caused by digital activity. Their advantages include small size, low power, no pipeline delay, and ease of use.Ī host processor can access or control the ADC via a variety of serial and parallel interfaces such as SPI, I 2C, and LVDS. ![]() Successive-approximation analog-to-digital converters, called SAR ADCs due to their successive-approximation register, are popular for applications requiring up to 18-bit resolution at up to 5 MSPS. Design Reliable Digital Interfaces for Successive-Approximation ADCs ![]()
0 Comments
Leave a Reply. |
AuthorWrite something about yourself. No need to be fancy, just an overview. ArchivesCategories |